1. Field of the Invention
The invention relates to the making of MOS transistors, a device comprising MOS transistors obtained by a method such as this and a device for the addressing and control of an active matrix made with devices such as these.
The invention pertains especially to an addressing and control device for an active matrix liquid crystal display.
The invention relates especially to the field of large-scale consumer electronics. It can be used to make electronic circuits with CMOS complementary transistors made of polycrystalline silicon. These transistors may comprise a lightly doped gate-edge region.
The invention can be applied to low-temperature methods (Tmax less than 450xc2x0 C.) compatible with non-refractory and non-crystalline substrates
2. Discussion of the Background
AMLCDs or Active Matrix Liquid Crystal Displays are made, according to prior art techniques, on a glass plate. The addressing of the active matrix liquid crystal displays is presently done by the integration of thin-film transistors on the glass plate. These TFT transistors are made out of amorphous hydrogenated silicon aSi:H. TFT transistors of this type have low electron mobility, in the range of 0,5 cm2 Vxe2x88x921 sxe2x88x921. The technology implemented to make them cannot be used to obtain a complementary logic circuitry. These constraints limit the use of such a technology to the making of the transistors needed to address the pixels of the screen. The management of the screen includes the selection of the lines, shaping and the presentation of the video. data on the different columns. The making of a device to carry out screen management requires the use of another technology, for example a technique to transfer silicon integrated circuits to the periphery of the glass slab.
To overcome the drawbacks of the technologies using amorphous silicon, the technologies are developing towards the use of thin-film polycrystalline silicon. The value attached to the use of thin-film polycrystalline silicon lies in the possibilities offered by this material for making high-quality electronic circuits on non-refractory and non-crystalline substrates.
The chief known applications lie in the addressing of active matrix liquid crystal displays.
Polycrystalline silicon enables the low-temperature manufacture of N type and P type TFTs with high values of mobility in the range of 100 and 50 cm2 Vxe2x88x921 sxe2x88x921 respectively. Polycrystalline silicon can therefore be used to make CMOS circuits with performance characteristics compatibles with the addressing of flat screens. The integration of all or part of the peripheral addressing electronics results in a relative decrease in the cost of the screen related to the disappearance of the integrated circuits. However, this is true only inasmuch as the increase in the complexity of the circuits made on the glass plate do not result in any major drop in manufacturing efficiency levels. The manufacturing efficiency is directly related to the number of masks used for the making of the electronic circuits.
The basic known method for the making of CMOS circuits on insulator substrates (for example of the SOI or Silicon On Insulator type) calls for at least six masks corresponding to the following steps:
definition of the silicon islands,
definition of the gate of the transistors,
definition of the N type implantation region,
definition of the P type implantation region,
opening of the contact holes,
definition of the metal.
The aim of the invention is to reduce the number of masks needed to make CMOS technology circuits as compared with known methods.
To this end, an object of the invention is a method for making transistors of a first type and a second type by CMOS technology in an active layer, characterized in that it consists in:
etching regions of the active layer or making them inactive so as to define active islands designed to form the sources, the channels of determined width and the drains of transistors of the first type and second type respectively,
covering at least the active islands with an insulating layer and then a conductive layer,
sequentially etching all the gates of the transistors of the first type and then all the gates of the transistors of the second type.
The gate of each transistor controls the transistor by enabling the control of the channel of this transistor.
The advantage of the method according to the invention is that it reduces the number of masks and the number of implantation steps.
In the basic known method, the gates of the NMOS and PMOS transistors are etched simultaneously. The N+ and P+ contact regions are obtained by ion implantation. They are self-aligned with respect to the gate edges: the gate plays the role of a mask. For the N type transistors, this situation leads to intense electrical fields in the gate edge channel. The intense electric fields induce either instability in the characteristics when the gate bias is positive or major leakage currents when the gate bias is negative. The instability of the characteristics is related to the generation of hot electrons in the channel and the creation of interface defects when these hot carriers interact with the hydrogen atoms, making the defects of the SiO2/Si interface passive. The leakage currents originate in the intense electrical field of the reverse-biased drain-channel junction. The level of the leakage currents then depends exponentially on the drain-source and gate-source voltages.
To attenuate these intense electrical fields, a particular region is made at the gate edge. This region has the characteristic of being more lightly doped than the rest of the channel. It is called an LDD region or lightly doped drain region. The LDD region is an Nxe2x88x92 type region for an N type transistor N. The extension of the LDD region is in the range of 10% of the length of the channel, i.e. about 0,1 xcexcm for monocrystalline silicon technologies and about 0,5 for polycrystalline silicon technologies. In monocrystalline technology, the LDD region is obtained by making a gate edge spacer or dielectric space. The spacer is obtained by appropriate deposition and anisotropic etching of a dielectric film. This technology is not directly applicable to large-surface substrates.
In known polycrystalline silicon technologies, the making of the LDD region requires a special mask and a particular step of implantation. This takes the number of masks needed to seven and the number of implantation steps to three. The invention reduces the number of masks needed to five and the number of implantation steps to two. The invention provides for a self-alignment of the LDD region and permits a check on the dose of dopant independently of the extension of the LDD region.
In the known polycrystalline silicon technologies, the LDD region is obtained by a light dose implantation self-aligned on the gate. After this, the LDD region is protected by resin during the heavy-dose implantation with dopant, namely N+ type implantation for an N type transistor, for example phosphorus. This may give rise to additional technological difficulties related to the heating of the resin under the flow of ions when the method is carried out on large-sized glass plates. This risk is totally absent in a method according to the invention. The layer of protective resin is removed before the heavy-dose implantation of a dopant.
An object of the invention is also a device for the addressing and control of an active matrix liquid crystal display made with CMOS transistors obtained by a method according to the invention.
The addressing and control device comprises an addressing device and a control device. The addressing device is a device with CMOS complementary transistors.
The control device is a device that does not require complementary transistors. It is preferably made with N type transistors. When these transistors are provided with an LDD region, according to a particular embodiment of the invention, they have the advantage of having a very limited leakage current. This characteristic is particularly important for large-sized active matrix screens. Each pixel of the screen is controlled by means of the gate of a transistor. Between two operations for refreshing a row of the matrix, the state of a pixel is held by means of the memory function obtained by the association of the capacitance of the pixel and the off state of the transistor, provided however, that the drain-source leakage current does not have the time to have any notable effect on the charge of the capacitance. Thus, the drain-source leakage current of the control transistors has an immediate effect on the quality of the image. In particular, the greater the drain-source leakage current, the more it results in a large